The present invention relates to a memory access control circuit for performing an access operation to a memory in response to a request from a data processing unit and, more particularly, to such a control circuit for a graphic controller in a graphic display system for displaying characters, figures and so forth by means of a printer and/or a raster scan type cathode ray tube (called hereinafter "CRT").
A memory access control circuit intervenes between a data processing unit and a memory and responds to an access request from the data processing unit to perform a data read/write operation on the memory in accordance with a designated one of various access modes.
Also in a graphics display system, a memory access control circuit intervenes between a drawing control unit, which performs a drawing data processing operation on characters, figures and so forth to be displayed, and a frame buffer memory, which temporarily stores character and figure data being currently displayed. The display of characters and figures on a CRT is performed by the drawing control unit which generates character and figure data to be displayed and writes them into the frame buffer memory through the memory access control circuit. While the access to the frame buffer memory is performed in word units, the actual drawing process is frequently performed only on one or few bits within the accessed word. This is because one pixel (picture element), which represents a unit of processing in the graphics display system, consists of one to four bits in general and thus one word includes a plurality of pixels. For instance, in drawing a line such as a straight line, a circle, an arc or the like, the number of pixels to be processed in one word is usually one (two or more in some cases). Therefore, only the data of a pixel or pixels to be processed within one word read out from the frame buffer memory are modified or updated in accordance with line type data and/or color data to be displayed and the word containing the modified or updated data bits is then written back to the same address of the buffer memory. In this case, three successive steps is required, the first step is reading one word of data from the frame buffer memory, the second step is modifying certain pixel data, and the third step is writing the word including modified data bits back to the memory. An operation for performing these three steps is hereinafter called "read-modify-write (or RMW) access".
On the other hand, such a memory has been developed and put into practical use, which has improved access modes for shortening access time. One of them is a write-per-bit (WPB) access mode. According to this access mode, by supplying the memory with only modifying data together with mask data for designating a bit or bits to be modified within one word, the data of the bit or bits designated by the mask data are automatically modified inside the memory in accordance with the modifying data. If the memory having WPB access is employed, therefore, the operation required of the graphic controller is reduced to only one step of supplying the modifying data and the mask data to the memory. The graphic controller is free from the data read access operation .and the data modifying operation. In other words, WPB access causes the same operation as RMW access with the same access speed as a random write access. WPB access is effective in the process of drawing a line above, in which the original data of the pixel or pixels to be processed are not required.
Another of the high-speed access modes is a page-mode access, in which a memory address is divided into a row address defined as a page address and a column address defined as a word address within a page so that the case of accessing successive words within one page, the row address for the second and later words is not required. The graphics display system also has a bit-block-transfer (BitBlt) function which transfers data stored in a certain area (i.e., a source area) to another area (i.e., a destination area), and thus the page-mode access is effective in this function.
Thus, by selecting the optimum access mode of the memories employed in the graphics display system in accordance with the drawing operation to be performed, the memory access speed and efficiency are greatly improved. The selection of the access mode to be used can be carried out by the drawing algorithms of the drawing control unit in response to the required drawing operations.
However, the kind of memory (and thus the access modes thereof) actually employed in a system depends on the specification of the system to be structured. That is, it is impossible for the drawing control unit to predict the kind of memory, which will be employed in the system, at the time of determining the drawing algorithms thereof. Moreover, in current systems, the memory, which is an object of the drawing operation by the drawing control unit, is not restricted to the frame buffer memory, but is spread over a so-called system memory which is used by CPU operating as the host processor of the system. Since the access frequency to the system memory by the CPU is considerably higher than that by the graphic controller, an ordinary dynamic memory (DRAM) not having WPB access mode is used as the system memory in view of the cost. Further, a system bus coupled with the system memory cannot generally meet the page-mode access requirements. Thus, there is one case where ordinary DRAMs are employed as both the frame buffer memory and the system memory, and another case where a memory having WPB access mode and/or the page-mode access is employed as the frame buffer memory and ordinary DRAM is employed as the system memory.
One approach is to prepare a plurality of drawing algorithms corresponding to the memory access modes for each one of the respective drawing operations. However, the preparation of a plurality of drawing algorithms causes the expansion of firmware for performing the respective algorithms, so that the cost of the drawing control unit is increased. Moreover, the unit is required to detect conditions and circumstances for selecting the optimum drawing algorithm, so that the burden of the application software is increased. Furthermore, if a new memory having a higher access speed mode is provided, the drawing control unit would have to be redesigned.